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64/256/512/1k/2k/4k/8k x 9 synchronous fifos cy7c4421/4201/4211/4221 cy7c4231/4241/4251 cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 document #: 38-06016 rev. *a revised march 6, 2202 features ? high-speed, low-power, first-in, first-out (fifo) memories ? 64 9 (cy7c4421) ? 256 9 (cy7c4201) ? 512 9 (cy7c4211) ? 1k 9 (cy7c4221) ? 2k 9 (cy7c4231) ? 4k 9 (cy7c4241) ? 8k 9 (cy7c4251) high-speed 100-mhz operation (10 ns read/write cycle time) low power (i cc = 35 ma) fully asynchronous and simultaneous read and write operation empty, full, and programmable almost empty and almost full status flags ttl-compatible expandable in width output enable (oe ) pin independent read and write enable pins center power and ground pins for reduced noise width-expansion capability space saving 7 mm 7 mm 32-pin tqfp 32-pin plcc pin-compatible and functionally equivalent to idt72421, 72201, 72211, 72221, 72231, and 72241 functional description the cy7c42x1 are high-speed, low-power fifo memories with clocked read and write interfaces. all are 9 bits wide. the cy7c42x1 are pin-compatible to idt722x1. programmable features include almost full/almost empty flags. these fifos provide solutions for a wide variety of data buffering needs, including high-speed data acquisition, multiprocessor inter- faces, and communications buffering. these fifos have 9-bit input and output ports that are controlled by separate clock and enable signals. the input port is controlled by a free-running clock (wclk) and two write-enable pins (wen1 , wen2/ld ). when wen1 is low and wen2/ld is high, data is written into the fifo on the rising edge of the wclk signal. while wen1 , wen2/ld is held active, data is continually written into the fifo on each wclk cycle. the output port is controlled in a similar manner by a free-running read clock (rclk) and two read-enable pins (ren1 , ren2 ). in addition, the cy7c42x1 has an output enable pin (oe ). the read (rclk) and write (wclk) clocks may be tied together for single-clock operation or the two clocks may be run independently for asynchronous read/write applications. clock frequencies up to 100 mhz are achievable. depth expansion is possible using one enable input for system control, while the other enable is controlled by expansion logic to direct the flow of data. logic block diagram pin configuration three-st ate output register read control flag logic write control write pointer read pointer reset logic input register flag program register d 0- 8 rclk ef pae paf q 0- 8 wen1 wclk rs oe dual port ram array 64 x 9 8k x 9 wen2/ld ren1 ren2 ff d 8 d 7 d 6 d 5 d 4 d 3 d 2 1 2 3 4 5 6 7 8 d 1 d 0 rclk gnd paf pae ren1 ren2 17 18 19 20 21 22 23 24 14 15 16 910111213 31 30 32 29 28 27 25 26 ff q 0 q 1 q 2 q 3 q 4 ef oe v cc wclk wen2/ld q 8 q 7 q 6 q 5 wen1 rs tqfp top view plcc d 1 d 0 rclk v cc d 8 d 7 d 6 d 5 d 4 d 3 gnd wclk wen2/ld q 8 q 7 d 2 paf pae 5 6 7 8 9 10 11 12 13 ren1 oe ren2 4321 3130 32 21 22 23 24 27 28 29 25 26 14 1516 17 181920 q 6 q 5 wen1 rs ff q 0 q 1 q 2 q 3 q 4 ef top view
cy7c4421/4201/4211/4221 cy7c4231/4241/4251 document #: 38-06016 rev. *a page 2 of 18 functional description the cy7c42x1 provides four status pins: empty, full, almost empty, almost full. the almost empty/almost full flags are programmable to single word granularity. the programmable flags default to empty ? 7 and full ? 7. the flags are synchronous, i.e., they change state relative to either the read clock (rclk) or the write clock (wclk). when entering or exiting the empty and almost empty states, the flags are updated exclusively by the rclk. the flags denoting almost full, and full states are updated exclusively by wclk. the synchronous flag architecture guarantees that the flags maintain their status for at least one cycle. all configurations are fabricated using advanced 0.65 n-well cmos technology. input esd protection is greater than 2001v, and latch-up is prevented by the use of guard rings. architecture the cy7c42x1 consists of an array of 64 to 8k words of 9 bits each (implemented by a dual-port array of sram cells), a read pointer, a write pointer, control signals (rclk, wclk, ren1 , ren2 , wen1 , wen2, rs ), and flags (ef , pae , paf , ff ). resetting the fifo upon power-up, the fifo must be reset with a reset (rs ) cycle. this causes the fifo to enter the empty condition signified by ef being low. all data outputs (q 0 ? 8 ) go low t rsf after the rising edge of rs . in order for the fifo to reset to its default state, a falling edge must occur on rs and the user must not read or write while rs is low. all flags are guaranteed to be valid t rsf after rs is taken low. fifo operation when the wen1 signal is active low and wen2 is active high, data present on the d 0 ? 8 pins is written into the fifo on each rising edge of the wclk signal. similarly, when the ren1 and ren2 signals are active low, data in the fifo memory will be presented on the q 0 ? 8 outputs. new data will be presented on each rising edge of rclk while ren1 and ren2 are active. ren1 and ren2 must set up t ens before rclk for it to be a valid read function. wen1 and wen2 must occur t ens before wclk for it to be a valid write function. an output enable (oe ) pin is provided to three-state the q 0 ? 8 outputs when oe is asserted. when oe is enabled (low), data in the output register will be available to the q 0 ? 8 outputs after t oe . the fifo contains overflow circuitry to disallow additional writes when the fifo is full, and underflow circuitry to disallow additional reads when the fifo is empty. an empty fifo maintains the data of the last valid read on its q 0 ? 8 outputs even after additional reads occur. write enable 1 (wen1 ) . if the fifo is configured for program- mable flags, write enable 1 (wen1 ) is the only write enable control pin. in this configuration, when write enable 1 (wen1 ) is low, data can be loaded into the input register and ram array on the low-to-high transition of every write clock (wclk). data is stored is the ram array sequentially and independently of any on-going read operation. write enable 2/load (wen2/ld ) . this is a dual-purpose pin. the fifo is configured at reset to have programmable flags or to have two write enables, which allows for depth expansion. if write enable 2/load (wen2/ld ) is set active high at reset (rs = low), this pin operates as a second write enable pin. if the fifo is configured to have two write enables, when write enable (wen1 ) is low and write enable 2/load (wen2/ld ) is high, data can be loaded into the input register and ram array on the low-to-high transition of every write clock (wclk). data is stored in the ram array sequentially and independently of any on-going read operation. programming when wen2/ld is held low during reset, this pin is the load (ld ) enable for flag offset programming. in this configuration, wen2/ld can be used to access the four 8-bit offset registers contained in the cy7c42x1 for writing or reading data to these registers. selection guide -10 -15 -25 unit maximum frequency 100 66.7 40 mhz maximum access time 8 10 15 ns minimum cycle time 10 15 25 ns minimum data or enable set-up 3 4 6 ns minimum data or enable hold 0.5 1 1 ns maximum flag delay 8 10 15 ns active power supply current commercial 35 35 35 icc1 industrial 40 40 40 cy7c4421 cy7c4201 cy7c4211 cy7c4221 cy7c4231 cy7c4241 cy7c4251 density 64 9 256 9 512 9 1k 9 2k 9 4k 9 8k 9
cy7c4421/4201/4211/4221 cy7c4231/4241/4251 document #: 38-06016 rev. *a page 3 of 18 when the device is configured for programmable flags and both wen2/ld and wen1 are low, the first low-to-high transition of wclk writes data from the data inputs to the empty offset least significant bit (lsb) register. the second, third, and fourth low-to-high transitions of wclk store data in the empty offset most significant bit (msb) register, full offset lsb register, and full offset msb register, respectively, when wen2/ld and wen1 are low. the fifth low-to-high transition of wclk while wen2/ld and wen1 are low writes data to the empty lsb register again. figure 1 shows the registers sizes and default values for the various device types. it is not necessary to write to all the offset registers at one time. a subset of the offset registers can be written; then by bringing the wen2/ld input high, the fifo is returned to normal read and write operation. the next time wen2/ld is brought low, a write operation stores data in the next offset register in sequence. the contents of the offset registers can be read to the data outputs when wen2/ld is low and both ren1 and ren2 are low. low-to-high transitions of rclk read register contents to the data outputs. writes and reads should not be preformed simultaneously on the offset registers. 64 9 256 9512 9 8 0 8 0 8 0 8 0 1k 9 2k 94k 98k 9 (msb) 0 (msb) 0 7 1 7 1 8 0 8 0 8 0 8 0 (msb) 00 (msb) 00 7 1 7 1 8 0 8 0 8 0 8 0 (msb) 000 (msb) 000 7 2 7 2 8 0 8 0 8 0 8 0 empty offset (lsb) reg. default value = 007h full offset (lsb) reg default value = 007h (msb) 0000 (msb) 0000 7 3 7 3 empty offset (lsb) reg. default value = 007h full offset (lsb) reg default value = 007h empty offset (lsb) reg. default value = 007h full offset (lsb) reg default value = 007h empty offset (lsb) reg. default value = 007h full offset (lsb) reg default value = 007h 8 0 8 0 8 0 8 0 empty offset (lsb) reg. default value = 007h full offset (lsb) reg default value = 007h (msb) 00000 (msb) 00000 7 4 7 4 8 0 8 0 8 0 8 0 65 65 full offset (lsb) reg default value = 007h empty offset (lsb) reg. default value = 007h 8 0 8 0 8 0 8 0 7 7 full offset (lsb) reg default value = 007h empty offset (lsb) reg. default value = 007h figure 1. offset register location and default values
cy7c4421/4201/4211/4221 cy7c4231/4241/4251 document #: 38-06016 rev. *a page 4 of 18 programmable flag (pae , paf ) operation whether the flag offset registers are programmed as described in table 1 or the default values are used, the programmable almost-empty flag (pae ) and programmable almost-full flag (paf ) states are determined by their corre- sponding offset registers and the difference between the read and write pointers. the number formed by the empty offset least significant bit register and empty offset most significant register is referred to as n and determines the operation of pae . pae is synchro- nized to the low-to-high transition of rclk by one flip-flop and is low when the fifo contains n or fewer unread words. pae is set high by the low-to-high transition of rclk when the fifo contains (n + 1) or greater unread words. the number formed by the full offset least significant bit register and full offset most significant bit register is referred to as m and determines the operation of paf . pae is synchro- nized to the low-to-high transition of wclk by one flip-flop and is set low when the number of unread words in the fifo is greater than or equal to cy7c4421. (64 ? m), cy7c4201 (256 ? m), cy7c4211 (512 ? m), cy7c4221 (1k ? m), cy7c4231 (2k ? m), cy7c4241 (4k ? m), and cy7c4251 (8k ? m). paf is set high by the low-to-high transition of wclk when the number of available memory locations is greater than m. table 1. writing the offset registers ld wen wclk [1] selection 0 0 empty offset (lsb) empty offset (msb) full offset (lsb) full offset (msb) 0 1 no operation 1 0 write into fifo 1 1 no operation table 2. status flags number of words in fifo ff paf pae ef cy7c4421 cy7c4201 cy7c4211 0 0 0 h h l l 1 to n [2] 1 to n [2] 1 to n [2] h h l h (n + 1) to 32 (n + 1) to 128 (n + 1) to 256 h h h h 33 to (64 ? (m + 1)) 129 to (256 ? (m + 1)) 257 to (512 ? (m + 1)) h h h h (64 ? m) [3] to 63 (256 ? m) [3] to 255 (512 ? m) [3] to 511 h l h h 64 256 512 l l h h number of words in fifo ff paf pae ef cy7c4221 cy7c4231 cy7c4241 cy7c4251 0 0 0 0 h h l l 1 to n [2] 1 to n [2] 1 to n [2] 1 to n [2] h h l h (n + 1) to 512 (n + 1) to 1024 (n + 1) to 2048 (n + 1) to 4096 h h h h 513 to (1024 ? (m + 1)) 1025 to (2048 ? (m + 1)) 2049 to (4096 ? (m + 1)) 4097 to (8192 ? (m + 1)) h h h h (1024 ? m) [3] to 1023 (2048 ? m) [3] to 2047 (4096 ? m) [3] to 4095 (8192 ? m) [3] to 8191 h l h h 1024 2048 4096 8192 l l h h notes: 1. the same selection sequence applies to reading from the registers. ren1 and ren2 are enabled and a read is performed on the low-to-high transition of rclk. 2. n = empty offset (n = 7 default value). 3. m = full offset (m = 7 default value).
cy7c4421/4201/4211/4221 cy7c4231/4241/4251 document #: 38-06016 rev. *a page 5 of 18 width expansion configuration word width may be increased simply by connecting the corre- sponding input controls signals of multiple devices. a composite flag should be created for each of the end-point status flags (ef and ff ). the partial status flags (pae and paf ) can be detected from any one device. figure 2 demon- strates a 18-bit word width by using two cy7c42x1s. any word width can be attained by adding additional cy7c42x1s. when the cy7c42x1 is in a width expansion configuration, the read enable (ren2 ) control input can be grounded (see figure 2 ). in this configuration, the write enable 2/load (wen2/ld ) pin is set to low at reset so that the pin operates as a control to load and read the programmable flag offsets. flag operation the cy7c42x1 devices provide four flag pins to indicate the condition of the fifo contents. empty, full, pae , and paf are synchronous. full flag the full flag (ff ) will go low when device is full. write opera- tions are inhibited whenever ff is low regardless of the state of wen1 and wen2/ld . ff is synchronized to wclk, i.e., it is exclusively updated by each rising edge of wclk. empty flag the empty flag (ef ) will go low when the device is empty. read operations are inhibited whenever ef is low, regardless of the state of ren1 and ren2 . ef is synchronized to rclk, i.e., it is exclusively updated by each rising edge of rclk. 42x1 ? 16 ff ff ef ef write clock (wclk) write enable 1 (wen1 ) write enable 2/load (wen2/ld) programmable (paf ) full flag (ff )# 1 cy7c42x1 9 18 data in (d) reset (rs ) 9 reset (rs ) read clock (rclk) read enable 1 (ren1 ) output enable (oe ) programmable (pae ) empty flag (ef ) #1 9 data out (q) 9 18 read enable 2 (ren2) cy7c42x1 empty flag (ef ) #2 full flag (ff )# 2 read enable 2 (ren2) figure 2. block diagram of 64 x 9, 256 x 9, 512 x 9, 1024 x 9, 2048 x 9, 4096 x 9, 8192 x 9 synchronous fifo memory used in a width expansion configuration
cy7c4421/4201/4211/4221 cy7c4231/4241/4251 document #: 38-06016 rev. *a page 6 of 18 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................... ? 65 c to +150 c ambient temperature with power applied............................................... ? 55 c to +125 c supply voltage to ground potential ............... ? 0.5v to +7.0v dc voltage applied to outputs in high-z state ............................................... ? 0.5v to +7.0v dc input voltage............................................ ? 3.0v to +7.0v output current into outputs (low)............................. 20 ma static discharge voltage .......................................... > 2001v (per mil-std-883, method 3015) latch-up current..................................................... > 200 ma operating range range ambient temperature v cc commercial 0 c to +70 c 5v 10% industrial [4] ? 40 c to +85 c 5v 10% pin definitions pin name i/o description d 0 ? 8 data inputs i data inputs for 9-bit bus q 0 ? 8 data outputs o data outputs for 9-bit bus wen1 write enable 1 i the only write enable to have programmable flags when device is configured. data is written on a low-to-high transition of wclk when wen1 is asserted and ff is high. if the fifo is configured to have two write enables, data is written on a low-to-high transition of wclk when wen1 is low and wen2/ld and ff are high. wen2/ld dual mode pin write enable 2 i if high at reset, this pin operates as a second write enable. if low at reset, this pin operates as a control to write or read the programmable flag offsets. wen1 must be low and wen2 must be high to write data into the fifo. data will not be written into the fifo if the ff is low. if the fifo is configured to have programmable flags, wen2/ld is held low to write or read the programmable flag offsets. load i ren1 , ren2 read enable inputs i enables device for read operation wclk write clock i the rising edge clocks data into the fifo when wen1 is low, wen2/ld is high, and the fifo is not full. when ld is asserted, wclk writes data into the programmable flag-offset register. rclk read clock i the rising edge clocks data out of the fifo when ren1 and ren2 are low and the fifo is not empty. when wen2/ld is low, rclk reads data out of the programmable flag-offset register. ef empty flag o when ef is low, the fifo is empty. ef is synchronized to rclk. ff full flag o when ff is low, the fifo is full. ff is synchronized to wclk. pae programmable almost empty o when pae is low, the fifo is almost empty based on the almost empty offset value pro- grammed into the fifo. paf programmable almost full o when paf is low, the fifo is almost full based on the almost full offset value programmed into the fifo. rs reset i resets device to empty condition. a reset is required before an initial read or write operation after power-up. oe output enable i when oe is low, the fifo ? s data outputs drive the bus to which they are connected. if oe is high, the fifo ? s outputs are in high-z (high-impedance) state. note: 4. t a is the ? instant on ? case temperature.
cy7c4421/4201/4211/4221 cy7c4231/4241/4251 document #: 38-06016 rev. *a page 7 of 18 electrical characteristics over the operating range [5] parameter description test conditions -10 -15 -25 unit min. max. min. max. min. max. v oh output high voltage v cc = min., i oh = ? 2.0 ma 2.4 2.4 2.4 v v ol output low voltage v cc = min., i ol = 8.0 ma 0.4 0.4 0.4 v v ih input high voltage 2.2 v cc 2.2 v cc 2.2 v cc v v il input low voltage ? 3.0 0.8 ? 3.0 0.8 ? 3.0 0.8 v i ix input leakage current v cc = max. ? 10 +10 ? 10 +10 ? 10 +10 a i os [6] output short circuit current v cc = max., v out = gnd ? 90 ? 90 ? 90 ma i ozl i ozh output off, high-z current oe > v ih , v ss < v o < v cc ? 10 +10 ? 10 +10 ? 10 +10 ma i cc1 [7] active power supply current commercial 35 35 35 ma industrial 40 40 40 ma i cc2 [8] average standby current commercial 10 10 10 ma industrial 15 15 15 ma capacitance [9] parameter description test conditions max. unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 5.0v 5 pf c out output capacitance 7 pf ac test loads and waveforms [10, 11] 3.0v 5v output r1 1.1 k ? r2 680 ? c l including jig and scope gnd 90% 10% 90% 10% 3ns 3 ns output 1.91v equivalent to: th venin equivalent 420 ? all input pulses switching characteristics over the operating range parameter description -10 -15 -25 unit min. max. min. max. min. max. t s clock cycle frequency 100 66.7 40 mhz t a data access time 2 8 2 10 2 15 ns t clk clock cycle time 10 15 25 ns t clkh clock high time 4.5 6 10 ns t clkl clock low time 4.5 6 10 ns t ds data set-up time 3 4 6 ns notes: 5. see the last page of this specification for group a subgroup testing information. 6. test no more than one output at a time for not more than one second. 7. outputs open. tested at frequency = 20 mhz. 8. all inputs = v cc ? 0.2v, except wclk and rclk, which are switching at 20 mhz. 9. tested initially and after any design or process changes that may affect these parameters. 10. c l = 30 pf for all ac parameters except for t ohz . 11. c l = 5 pf for t ohz .
cy7c4421/4201/4211/4221 cy7c4231/4241/4251 document #: 38-06016 rev. *a page 8 of 18 t dh data hold time 0.5 1 1 ns t ens enable set-up time 3 4 6 ns t enh enable hold time 0.5 1 1 ns t rs reset pulse width [12] 10 15 25 ns t rss reset set-up time 8 10 15 ns t rsr reset recovery time 8 10 15 ns t rsf reset to flag and output time 10 15 25 ns t olz output enable to output in low-z [13] 0 0 0 ns t oe output enable to output valid 3 7 3 8 3 12 ns t ohz output enable to output in high-z [13] 3 7 3 8 3 12 ns t wff write clock to full flag 8 10 15 ns t ref read clock to empty flag 8 10 15 ns t paf clock to programmable almost-full flag 8 10 15 ns t pae clock to programmable almost-full flag 8 10 15 ns t skew1 skew time between read clock and write clock for empty flag and full flag 5 6 10 ns t skew2 skew time between read clock and write clock for almost-empty flag and almost-full flag 10 15 18 ns switching characteristics over the operating range parameter description -10 -15 -25 unit min. max. min. max. min. max. switching waveforms notes: 12. pulse widths less than minimum values are not allowed. 13. values guaranteed by design, not currently tested. write cycle timing t clkh t clkl no operation t ds t skew1 t ens wen1 t clk t dh t wff t wff t enh wclk d 0 ? d 8 ff ren1 ,ren2 rclk no operation wen2 (if applicable) [14]
cy7c4421/4201/4211/4221 cy7c4231/4241/4251 document #: 38-06016 rev. *a page 9 of 18 notes: 14. t skew1 is the minimum time between a rising rclk edge and a rising wclk edge to guarantee that ff will go high during the current clock cycle. if the time between the rising edge of rclk and the rising edge of wclk is less than t skew1 , then ff may not change state until the next wclk rising edge. 15. t skew1 is the minimum time between a rising wclk edge and a rising rclk edge to guarantee that ef will go high during the current clock cycle. it the time between the rising edge of wclk and the rising edge of rclk is less than t skew1 , then ef may not change state until the next rclk rising edge. switching waveforms (continued) ren1 ,ren2 read cycle timing t clkh t clkl no operation t skew1 wen1 t ckl t ohz t ref t ref rclk q 0 ? q 8 ef wclk oe t oe t ens t olz t a t enh valid data wen2 [15] t rs t rsr q 0- q 8 rs t rsf t rsf t rsf o e =1 oe=0 ren1 , ren2 ef ,pae ff , paf , t rss t rsr t rss t rsr t rss wen2/ld wen1 reset timing [16] [17] [18]
cy7c4421/4201/4211/4221 cy7c4231/4241/4251 document #: 38-06016 rev. *a page 10 of 18 notes: 16. the clocks (rclk, wclk) can be free-running during reset. 17. holding wen2/ld high during reset will make the pin act as a second enable pin. holding wen2/ld low during reset will make the pin act as a load enable for the programmable flag offset registers. 18. after reset, the outputs will be low if oe = 0 and three-state if oe =1. 19. when t skew1 > minimum specification, t frl (maximum) = t clk + t skew1 . when t skew1 < minimum specification, t frl (maximum) = either 2*t clk + t skew1 or t clk + t skew1 . the latency timing applies only at the empty boundary (ef = low). 20. the first word is available the cycle after ef goes high, always. switching waveforms (continued) d 0 (first valid write) first data word latency after reset with simultaneous read and write t skew1 wen1 wclk q 0 ? q 8 ef ren1 , ren2 oe t oe t ens t olz t ds rclk t ref t a t frl d 1 d 2 d 3 d 4 d 0 d 1 d 0 ? d 8 t a wen2 (if applicable) [19] [20] datawrite2 datawrite1 t ens t skew1 data in output register empty flag timing wen1 wclk q 0 ? q 8 ef ren1 , ren2 oe t ds t enh rclk t ref t a t frl d 0 ? d 8 data read t skew1 t frl t ref t ds t ens t enh wen2 (if applicable) t ref low [19] [19] t ens t ens t enh t enh
cy7c4421/4201/4211/4221 cy7c4231/4241/4251 document #: 38-06016 rev. *a page 11 of 18 switching waveforms (continued) full flag timing q 0 ? q 8 ren1 , ren2 wen1 wen2 (if applicable) d 0 ? d 8 next data read data write no write data in output register ff wclk oe rclk t a data read t skew1 t ds t ens t enh t wff t a t skew1 t ens t enh t wff data write no write t wff low no write [14] [14] t enh programmable almost empty flag timing wclk pae rclk t clkh t ens t clkl t ens t pae n + 1 words infifo t enh t ens t enh t ens t pae ren1 , ren2 wen1 wen2 (if applicable) t skew2 [21] note 22 note 23
cy7c4421/4201/4211/4221 cy7c4231/4241/4251 document #: 38-06016 rev. *a page 12 of 18 notes: 21. t skew2 is the minimum time between a rising wclk and a rising rclk edge for pae to change state during that clock cycle. if the time between the edge of wclk and the rising rclk is less than t skew2 , then pae may not change state until the next rclk. 22. pae offset = n. 23. if a read is performed on this rising edge of the read clock, there will be empty + (n ? 1) words in the fifo when pae goes low. 24. if a write is performed on this rising edge of the write clock, there will be full ? (m ? 1) words of the fifo when paf goes low. 25. paf offset = m. 26. 64-m words for cy7c4421, 256 ? m words in fifo for cy7c4201, 512 ? m words for cy7c4211, 1024 ? m words for cy7c4221, 2048 ? m words for cy7c4231, 4096 ? m words for cy7c4241, 8192 ? m words for cy7c4251. 27. t skew2 is the minimum time between a rising rclk edge and a rising wclk edge for paf to change during that clock cycle. if the time between the rising edge of rclk and the rising edge of wclk is less than t skew2 , then paf may not change state until the next wclk. switching waveforms (continued) t enh programmable almost full flag timing wclk paf rclk t clkh t ens full ? m words in fifo t clkl t ens full ? m+1 words in fifo t enh t ens t enh t ens t paf ren1 , ren2 wen1 wen2 (if applicable) t skew2 t paf note 24 note 25 [26] [27] t enh write programmable registers wen2/ld wclk t clkh t ens t clkl pae offset lsb d 0 ? d 8 wen1 t ens paf offset msb t clk t ds t dh pae offset msb paf offset lsb
cy7c4421/4201/4211/4221 cy7c4231/4241/4251 document #: 38-06016 rev. *a page 13 of 18 switching waveforms (continued) paf offset msb paf offset lsb t enh read programmable registers wen2/ld rclk t clkh t ens t clkl pae offset lsb q 0 ? q 8 ren1 , ren2 t ens pae offset msb t clk unknown t a
cy7c4421/4201/4211/4221 cy7c4231/4241/4251 document #: 38-06016 rev. *a page 14 of 18 typical ac and dc characteristics supply voltage (v) normalized t a vs. supply voltage normalized supply current vs. supply voltage normalized t a vs. ambient temperature normalized supply current vs. ambient temperature frequency (mhz) normalized supply current vs. frequency supply voltage (v) 0.50 0.75 1.00 1.25 1.50 v cc = 5.0v normalized i cc normalized i cc ambient temperature ( c) v in = 3.0v t a = 25 c f = 100 mhz 0.80 0.90 1.00 1.10 1.20 normalized i cc 0.60 0.70 0.80 0.90 1.00 1.10 v cc = 5.0v t a = 25 c v in = 3.0v capacitance (pf) delta t a (ns) typical t a change vs. output loading v cc = 5.0v t a = 25 c output source current vs. output voltage output voltage (v) output sink current vs. output voltage output voltage (v) output source current (ma) output sink current (ma) normalized t a ambient temperature ( c) normalized t a 12 34 01234 0 0 25 50 75 100 0 200 400 600 800 1000 4 4.5 5 5.5 6 ? 55 25 125 ? 55 25 125 v in = 3.0v v cc = 5.0v f = 100 mhz 0.6 0.8 1.0 1.2 1.4 0.9 1.0 1.1 1.2 0.8 4 4.5 5 5.5 6 0 20 40 60 80 100 120 140 160 45 35 25 55 0 10 25 40
cy7c4421/4201/4211/4221 cy7c4231/4241/4251 document #: 38-06016 rev. *a page 15 of 18 ordering information 64 x 9 synchronous fifo speed (ns) ordering code package name package type operating range 10 cy7c4421-10ac a32 32-lead thin quad flatpack commercial cy7c4421-10jc j65 32-lead plastic leaded chip carrier 15 cy7c4421-15ac a32 32-lead thin quad flatpack commercial cy7c4421-15jc j65 32-lead plastic leaded chip carrier 256 x 9 synchronous fifo speed (ns) ordering code package name package type operating range 10 cy7c4201-10ac a32 32-lead thin quad flatpack commercial cy7c4201-10jc j65 32-lead plastic leaded chip carrier 15 cy7c4201-15ac a32 32-lead thin quad flatpack commercial cy7c4201-15jc j65 32-lead plastic leaded chip carrier 25 cy7c4201-25ac a32 32-lead thin quad flatpack commercial cy7c4201-25jc j65 32-lead plastic leaded chip carrier cy7C4201-25AI a32 32-lead thin quad flatpack industrial 512 x 9 synchronous fifo speed (ns) ordering code package name package type operating range 10 cy7c4211-10ac a32 32-lead thin quad flatpack commercial cy7c4211-10jc j65 32-lead plastic leaded chip carrier cy7c4211-10ai a32 32-lead thin quad flatpack industrial cy7c4211-10ji j65 32-lead plastic leaded chip carrier 15 cy7c4211-15ac a32 32-lead thin quad flatpack commercial cy7c4211-15jc j65 32-lead plastic leaded chip carrier cy7c4211-15ai a32 32-lead thin quad flatpack industrial 25 cy7c4211-25ac a32 32-lead thin quad flatpack commercial cy7c4211-25jc j65 32-lead plastic leaded chip carrier 1k x 9 synchronous fifo speed (ns) ordering code package name package type operating range 10 cy7c4221-10ac a32 32-lead thin quad flatpack commercial cy7c4221-10jc j65 32-lead plastic leaded chip carrier 15 cy7c4221-15ac a32 32-lead thin quad flatpack commercial cy7c4221-15jc j65 32-lead plastic leaded chip carrier 25 cy7c4221-25ac a32 32-lead thin quad flatpack commercial cy7c4221-25jc j65 32-lead plastic leaded chip carrier 2k x 9 synchronous fifo speed (ns) ordering code package name package type operating range 10 cy7c4231-10ac a32 32-lead thin quad flatpack commercial cy7c4231-10jc j65 32-lead plastic leaded chip carrier 15 cy7c4231-15ac a32 32-lead thin quad flatpack commercial
cy7c4421/4201/4211/4221 cy7c4231/4241/4251 document #: 38-06016 rev. *a page 16 of 18 cy7c4231-15jc j65 32-lead plastic leaded chip carrier 25 cy7c4231-25ac a32 32-lead thin quad flatpack commercial cy7c4231-25jc j65 32-lead plastic leaded chip carrier 4k x 9 synchronous fifo speed (ns) ordering code package name package type operating range 10 cy7c4241-10ac a32 32-lead thin quad flatpack commercial cy7c4241-10jc j65 32-lead plastic leaded chip carrier cy7c4241-10ji j65 32-lead plastic leaded chip carrier industrial 15 cy7c4241-15ac a32 32-lead thin quad flatpack commercial cy7c4241-15jc j65 32-lead plastic leaded chip carrier 25 cy7c4241-25ac a32 32-lead thin quad flatpack commercial cy7c4241-25jc j65 32-lead plastic leaded chip carrier cy7c4241-25ji j65 32-lead plastic leaded chip carrier industrial 8k x 9 synchronous fifo speed (ns) ordering code package name package type operating range 10 cy7c4251-10ac a32 32-lead thin quad flatpack commercial cy7c4251-10jc j65 32-lead plastic leaded chip carrier cy7c4251-10ai a32 32-lead thin quad flatpack industrial 15 cy7c4251-15ac a32 32-lead thin quad flatpack commercial cy7c4251-15jc j65 32-lead plastic leaded chip carrier 25 cy7c4251-25ac a32 32-lead thin quad flatpack commercial cy7c4251-25jc j65 32-lead plastic leaded chip carrier cy7c4251-25ai a32 32-lead thin quad flatpack industrial 2k x 9 synchronous fifo (continued) speed (ns) ordering code package name package type operating range
cy7c4421/4201/4211/4221 cy7c4231/4241/4251 document #: 38-06016 rev. *a page 17 of 18 ? cypress semiconductor corporation, 2002. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do i ng so indemnifies cypress semiconductor against all charges. all product and company names mentioned in this document may be the trademarks of their respective holders. package diagrams 32-lead thin plastic quad flatpack 7 7 1.0 mm a32 51-85063-b 32-lead plastic leaded chip carrier j65 51-85002-b
cy7c4421/4201/4211/4221 cy7c4231/4241/4251 document #: 38-06016 rev. *a page 18 of 18 document title: cy7c4421/4201/4211/4221, cy7c4231/4241/4251 64/256/512/1k/2k/4k/8k x 9 synchronous fifos document number: 38-06016 rev. ecn no. issue date orig. of change description of change ** 106477 09/10/01 szv change from spec number: 38-00419 to 38-06016 *a 110725 03/20/02 fsg change input leakage current i ix unit from ma to a (typo)

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